Marking pattern in forming staircase structure of three-dimensional memory device
US11121092B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 16, 2019 |
| Grant date | Sep 14, 2021 |
| Priority date | — |
| Expiry date | Aug 16, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/10
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments of a marking pattern in forming the staircase structure of a three-dimensional (3D) memory device are provided. In an example, a semiconductor device includes a stack structure having a plurality of insulating layers and a plurality of conductor layers arranged alternatingly over a substrate along a vertical direction. In some embodiments, the semiconductor device also includes a marking pattern having a plurality of interleaved layers of different materials over the substrate and neighboring the stack structure. The marking pattern includes a central marking structure located in a marking area, the central marking structure dividing the marking area into a first marking sub-area farther from the stack structure and a second marking sub-area closer to the stack structure, a first pattern density of the first marking sub-area being higher than or equal to a second pattern density of the second marking sub-area.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.