Memory structure and manufacturing method therefor
US11121142B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 31, 2019 |
| Grant date | Sep 14, 2021 |
| Priority date | — |
| Expiry date | Feb 2, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/528
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a memory structure including the following steps is provided. A spacer layer is formed on sidewalls of gate stack structures. A protective material layer covering the spacer layer and the gate stack structures is formed. A mask material layer is formed on the protective material layer. There is a void located in the mask material layer between two adjacent gate stack structures. A first distance is between a top of the protective material layer and a top of the mask material layer. A second distance is between a top of the void and a top of the mask material layer above the void. A third distance is between a bottom of the void and a bottom of the mask material layer below the void. The first distance is greater than a sum of the second and third distances.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.