Semiconductor device integrating backside power grid and related integrated circuit and fabrication method
US11121256B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 5, 2020 |
| Grant date | Sep 14, 2021 |
| Priority date | — |
| Expiry date | Jun 5, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6219
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming a non-planar semiconductor device includes: forming a fin structure protruding from a front side of a substrate of the non-planar semiconductor device; depositing a dielectric region on the front side of the substrate, the dielectric region including a conductive rail buried within the dielectric region and in parallel with the fin structure; etching the dielectric region to create a first opening in the dielectric region to expose the conductive rail; depositing a plurality of conductive regions on the dielectric region, one of the conductive regions contacting the conductive rail through the first opening; etching the substrate from a backside of the substrate to form a second opening to expose the conductive rail; and filling a first conductive material into the second opening to form a through-substrate via in the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.