Sidewall spacer structure for memory cell

US11121308B2 · kind B2 · utility

Assignee

• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. · TW

Inventors

• Yao-Wen Chang · Hsinchu, TW
• Chung-Chiang Min · Hengshan, TW
• Harry-Hak-Lay Chuang · Austin, US
• Hung Cho Wang · Taipei, TW
• Tsung-Hsueh Yang · Taichung, TW
• Yuan-Tai Tseng · Dashulong, TW
• Sheng-Huang Huang · Hsinchu, TW
• Chia-Hua Lin · Baoshan, TW

Key dates

• Filing date: Oct 15, 2019
• Grant date: Sep 14, 2021
• Expiry date: Oct 30, 2039

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10N50/10

Abstract

Various embodiments of the present disclosure are directed towards an integrated chip including a magnetoresistive random access memory (MRAM) cell over a substrate. A dielectric structure overlies the substrate. The MRAM cell is disposed within the dielectric structure. The MRAM cell includes a magnetic tunnel junction (MTJ) sandwiched between a bottom electrode and a top electrode. A conductive wire overlies the top electrode. A sidewall spacer structure continuously extends along a sidewall of the MTJ and the top electrode. The sidewall spacer structure includes a first sidewall spacer layer, a second sidewall spacer layer, and a protective sidewall spacer layer sandwiched between the first and second sidewall spacer layers. The first and second sidewall spacer layers comprise a first material and the protective sidewall spacer layer comprises a second material different than the first material.