Preparation of solder bump for compatibility with printed electronics and enhanced via reliability
US11122692B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 11, 2020 |
| Grant date | Sep 14, 2021 |
| Priority date | — |
| Expiry date | Jun 11, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2203/046
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A process of fabricating a circuit includes providing a first sheet of dielectric material including a first top surface having at least one first conductive trace and a second sheet of dielectric material including a second top surface having at least one second conductive trace, depositing a first solder bump on the at least one first conductive trace, applying the second sheet of dielectric material to the first sheet of dielectric material with bonding film sandwiched in between, bonding the first and second sheets of dielectric material to one another, and providing a conductive material to connect the first solder bump on the at least one first conductive trace to the at least one second conductive trace.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.