Fan-out semiconductor package
US11127646B2 · kind B2 · utility
1Cited by
1References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 12, 2019 |
| Grant date | Sep 21, 2021 |
| Priority date | — |
| Expiry date | Nov 12, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A fan-out semiconductor package includes a semiconductor chip, an encapsulant covering the semiconductor chip, a connection structure disposed below the semiconductor chip, and first and second metal pattern layers disposed on different levels on the semiconductor chip, wherein the first metal pattern layer is provided to electrically connect to an electrical connection member such as a frame, provided for electrical connection of the package in a vertical direction by a path via the second metal pattern layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.