Semiconductor package
US11127692B2 · kind B2 · utility
0Cited by
1References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 24, 2019 |
| Grant date | Sep 21, 2021 |
| Priority date | — |
| Expiry date | Sep 12, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package includes a semiconductor chip, and a connection structure disposed on at least one side of the semiconductor chip, and including an insulating layer and a redistribution layer electrically connected to the semiconductor chip, wherein the redistribution layer includes a plurality of conductive patterns, and at least two of the plurality of conductive patterns have different degrees of surface roughness, and a conductive pattern having a higher surface roughness has a width wider than a width of a conductive pattern having a lower surface roughness.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.