Board defect filtering method based on defect list and circuit layout image and device thereof and computer-readable recording medium
US11132786B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 19, 2018 |
| Grant date | Sep 28, 2021 |
| Priority date | — |
| Expiry date | Mar 20, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T2207/30141
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A board defect filtering method is provided. The method includes: receiving a defect list; obtaining a plurality of defect images of a plurality of defect records on the defect list; receiving a circuit layout image; analyzing a defect location of a first defect image of the plurality of defect images according to the circuit layout image; cropping the first defect image to obtain a first cropped defect image according to the defect location; inputting the first cropping defect image to a defect classifying model; and determining whether the first defect image is a qualified product image or not according to an output result of the defect classifying model.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.