Power switch control in a memory device
US11133039B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 7, 2019 |
| Grant date | Sep 28, 2021 |
| Priority date | — |
| Expiry date | Nov 5, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/417
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A power switch control circuit includes a supply rail configured to supply power to a memory array. A first header switch couples the supply rail to a first power supply that corresponds to a first power domain. A second header switch couples the supply rail to a second power supply that corresponds to a second power domain. A control circuit is configured to receive a select signal and a shutdown signal, and to output control signals to the first and second header switches to selectively couple the first and second header switches to the first and second power supplies, respectively, in response to the select signal and the shutdown signal. The control circuit is configured to output the control signals to the first and second header switches to disconnect both the first and second header switches from the first and second power supplies in response to the shutdown signal and irrespective of the select signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.