Latch-type sense amplifier for a non-volatile memory with reduced margin between supply voltage and bitline-selection voltage
US11133064B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 16, 2020 |
| Grant date | Sep 28, 2021 |
| Priority date | — |
| Expiry date | Jul 16, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2013/0054
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A sense amplifier and a method for accessing a memory device are disclosed. In an embodiment a sense amplifier for a memory device includes a first input node selectively coupled to a first memory cell through a first local bitline and a first main bitline, a second input node selectively coupled through a second local bitline and a second main bitline to a second memory cell or to a reference generator configured to generate a reference current, a first current generator controllable so as to inject a first variable current into the first input node, a second current generator controllable so as to inject a second variable current into the second input node, a first branch coupled to the first input node and comprising a first switch circuit, a first sense transistor and a first forcing transistor and a second branch coupled to the second input node and including a second switch circuit, a second sense transistor and a second forcing transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.