Memory device and test operation method thereof
US11133080B2 · kind B2 · utility
1Cited by
17References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 26, 2019 |
| Grant date | Sep 28, 2021 |
| Priority date | — |
| Expiry date | Dec 26, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/1206
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present technology includes a memory device and a method of operating the same. The memory device in which an interface circuit and a semiconductor memory are packaged together includes a centrally located region in a ball mapping region of a memory device in which data input/output pins for an operation of the interface circuit and the semiconductor memory are disposed, and a test pin region in which test pins for a test operation of the interface circuit are disposed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.