Method for manufacturing semiconductor structure
US11133222B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 6, 2019 |
| Grant date | Sep 28, 2021 |
| Priority date | — |
| Expiry date | May 6, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/015
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods of manufacturing a semiconductor structure are provided. One of the methods includes the following operations. A substrate is received, and the substrate includes a first transistor with a first conductive region and a second transistor with a second conductive region, wherein the first transistor and the second transistor have different conductive types. A first laser anneal is performed on the first conductive region to repair lattice damage. An amorphization is performed on the first conductive region and the second conductive region to enhance silicide formation to a desired phase transformation in the subsequent operations. A pre-silicide layer is formed on the substrate after the amorphization. A thermal anneal is performed to the substrate to form a silicide layer from the pre-silicide layer. A second laser anneal is performed on the first conductive region and the second conductive region after the formation of the pre-silicide layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.