Multi-layer fin structure
US11133386B2 · kind B2 · utility
0Cited by
18References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 6, 2020 |
| Grant date | Sep 28, 2021 |
| Priority date | — |
| Expiry date | Jan 6, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/017
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure provides one embodiment of a semiconductor structure. The structure includes a semiconductor substrate; a fin extending above the semiconductor substrate, wherein the fin includes a first layer over the semiconductor substrate and a second layer over the first layer, wherein the first layer includes silicon germanium having a first concentration of germanium, and wherein the second layer includes silicon germanium having a second concentration of germanium less than the first concentration of germanium; and a gate stack disposed over the fin.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.