Dielectric passivation for layered structures
US11133408B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 6, 2019 |
| Grant date | Sep 28, 2021 |
| Priority date | — |
| Expiry date | Feb 27, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/8503
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A passivated semiconductor device structure includes a III-nitride structure and a passivation layer. The III-nitride structure includes a high electron mobility transistor (HEMT). The passivation layer includes a dielectric, which is formed over the structure to provide passivation and forms an interface with the structure. The interface provides a transition between the structure and the dielectric having a thickness of at least two atomic layers. The interface also has a characteristic density of interface states less than a reference density of interface states that corresponds to a thickness of at most one atomic layer. The transition, which constitutes a rough interface, allows a relatively low density of interface states, and thus improves high-frequency performance of the device structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.