Methods of forming semiconductor devices having plural epitaxial layers
US11133416B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 23, 2019 |
| Grant date | Sep 28, 2021 |
| Priority date | — |
| Expiry date | Oct 28, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/021
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In an embodiment, a device includes: a fin extending from a substrate; a gate stack over a channel region of the fin; and a source/drain region in the fin adjacent the channel region, the source/drain region including: a first epitaxial layer contacting sidewalls of the fin, the first epitaxial layer including silicon and germanium doped with a dopant, the first epitaxial layer having a first concentration of the dopant; and a second epitaxial layer on the first epitaxial layer, the second epitaxial layer including silicon and germanium doped with the dopant, the second epitaxial layer having a second concentration of the dopant, the second concentration being greater than the first concentration, the first epitaxial layer and the second epitaxial layer having a same germanium concentration.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.