Techniques for processor queue management
US11134021B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 29, 2016 |
| Grant date | Sep 28, 2021 |
| Priority date | — |
| Expiry date | May 1, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L47/39
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Techniques and apparatus for processor queue management are described. In one embodiment, for example, an apparatus to provide queue congestion management assistance may include at least one memory and logic for a queue manager, at least a portion of the logic comprised in hardware coupled to the at least one memory, the logic to determine queue information for at least one queue element (QE) queue storing at least one QE, compare the queue information to at least one queue threshold value, and generate a queue notification responsive to the queue information being outside of the queue threshold value. Other embodiments are described and claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.