Debra Bernstein
79Patents
27h-index
72Co-inventors
91Inventor score
Filing activity: Apr 1, 1988 → Dec 26, 2020
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6694380B1 | Mapping requests from a processing unit that uses memory-mapped input-output space | Physics | 157 | Expired |
| US6625654B1 | Thread signaling in multi-threaded network processor | Physics | 121 | Expired |
| US6668317B1 | Microengine for parallel processor architecture | Physics | 121 | Expired |
| US6532509B1 | Arbitrating command requests in a parallel multi-threaded processing system | Physics | 94 | Expired |
| US6661794B1 | Method and apparatus for gigabit packet assignment for multithreaded packet processing | Electricity | 93 | Expired |
| US6868476B2 | Software controlled content addressable memory in a general purpose execution datapath | Physics | 76 | Expired |
| US6560667B1 | Handling contiguous memory references in a multi-queue system | Physics | 75 | Expired |
| US6324624A | Read lock miss control and queue management | Physics | 71 | Expired |
| US6463072B1 | Method and apparatus for sharing access to a bus | Electricity | 70 | Expired |
| US6667920B2 | Scratchpad memory | Physics | 69 | Expired |
| US6587906B2 | Parallel multi-threaded processing | Physics | 67 | Expired |
| US6631462B1 | Memory shared between processing threads | Physics | 66 | Expired |
| US6307789A | Scratchpad memory | Physics | 65 | Expired |
| US7366865B2 | Enqueueing entries in a packet queue referencing packets | Physics | 64 | Expired |
| US7216204B2 | Mechanism for providing early coherency detection to enable high performance memory updates in a latency sensitive multithreaded environment | Physics | 61 | Expired |
| US6584522B1 | Communication between processors | Physics | 61 | Expired |
| US6681300B2 | Read lock miss control and queue management | Physics | 61 | Expired |
| US6577542B2 | Scratchpad memory | Physics | 59 | Expired |
| US6631430B1 | Optimizations to receive packet status from fifo bus | Emerging Cross-Sectional Technologies | 58 | Expired |
| US5542058A | Pipelined computer with operand context queue to simplify context-dependent execution flow | Mechanical Engineering; Lighting; Heating | 43 | Expired |
| US7020871B2 | Breakpoint method for parallel hardware threads in multithreaded processor | Physics | 42 | Expired |
| US6976095B1 | Port blocking technique for maintaining receive packet ordering for a multiple ethernet port switch | Electricity | 42 | Expired |
| US6934951B2 | Parallel processor with functional pipeline providing programming engines by supporting multiple contexts and critical section | Physics | 37 | Expired |
| US7111296B2 | Thread signaling in multi-threaded processor | Physics | 33 | Expired |
| US7546444B1 | Register set used in multithreaded parallel processor architecture | Physics | 30 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.