Providing dynamic selection of cache coherence protocols in processor-based devices
US11138114B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 8, 2020 |
| Grant date | Oct 5, 2021 |
| Priority date | — |
| Expiry date | Jan 8, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/1016
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Providing dynamic selection of cache coherence protocols in processor-based devices is disclosed. In this regard, a processor-based device includes a master PE and at least one snooper PE, as well as a central ordering point (COP). The COP dynamically selects, on a store-by-store basis, either a write invalidate protocol or a write update protocol as a cache coherence protocol to use for maintaining cache coherency for a memory store operation by the master PE. The selection is made by the COP based on one or more protocol preference indicators that may be generated and provided by one or more of the master PE, the at least one snooper PE, and the COP itself. After selecting the cache coherence protocol to use, the COP sends a response message to each of the master PE and the at least one snooper PE indicating the selected cache coherence protocol.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.