Derek T. Bachand
30Patents
10h-index
23Co-inventors
75Inventor score
Filing activity: Dec 29, 1997 → Sep 18, 2020
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6499090B1 | Prioritized bus request scheduling mechanism for processing devices | Physics | 66 | Expired |
| US6321297A | Avoiding tag compares during writes in multi-level cache hierarchy | Physics | 54 | Expired |
| US6732242B2 | External bus transaction scheduling system | Physics | 49 | Expired |
| US7487305B2 | Prioritized bus request scheduling mechanism for processing devices | Physics | 48 | Active |
| US6668309B2 | Snoop blocking for cache coherency | Physics | 27 | Expired |
| US6216208A | Prefetch queue responsive to read request sequences | Physics | 25 | Expired |
| US6078981A | Transaction stall technique to prevent livelock in multiple-processor systems | Physics | 22 | Expired |
| US6782457B2 | Prioritized bus request scheduling mechanism for processing devices | Physics | 20 | Expired |
| US6606692B2 | Prioritized bus request scheduling mechanism for processing devices | Physics | 19 | Expired |
| US6378048B1 | “SLIME” cache coherency system for agents with multi-layer caches | Physics | 15 | Expired |
| US6209068A | Read line buffer and signaling protocol for processor | Physics | 10 | Expired |
| US6578116B2 | Snoop blocking for cache coherency | Physics | 8 | Expired |
| US6434677B1 | Method and apparatus for altering data length to zero to maintain cache coherency | Physics | 7 | Expired |
| US6460119B1 | Snoop blocking for cache coherency | Physics | 7 | Expired |
| US6578114B2 | Method and apparatus for altering data length to zero to maintain cache coherency | Physics | 6 | Expired |
| US6654837B1 | Dynamic priority external transaction system | Physics | 5 | Expired |
| US6735675B2 | Method and apparatus for altering data length to zero to maintain cache coherency | Physics | 5 | Expired |
| US8205111B2 | Communicating via an in-die interconnect | Physics | 4 | Active |
| US7133981B2 | Prioritized bus request scheduling mechanism for processing devices | Physics | 4 | Expired |
| US7143242B2 | Dynamic priority external transaction system | Physics | 4 | Expired |
| US6401172B1 | Recycle mechanism for a processing agent | Physics | 3 | Expired |
| US6412091B2 | Error correction system in a processing agent having minimal delay | Electricity | 2 | Expired |
| US6269465A | Error correction system in a processing agent having minimal delay | Electricity | 2 | Expired |
| US7555603B1 | Transaction manager and cache for processing agent | Physics | 1 | Expired |
| US11372757B2 | Tracking repeated reads to guide dynamic selection of cache coherence protocols in processor-based devices | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.