Hardware-based coherency checking techniques
US11138115B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 4, 2020 |
| Grant date | Oct 5, 2021 |
| Priority date | — |
| Expiry date | Apr 8, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7208
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods, systems, and devices for hardware-based coherency checking techniques are described. A memory sub-system with hardware-based coherency checking can include a coherency block that maintains a coherency lock and releases coherency upon completion of a write command. The coherency block can perform operations to lock coherency associated with the write command, monitor for completion of the write to the memory device(s), release the coherency lock, and update one or more records used to monitor coherency associated with the write command. A coherency command and coherency status can be provided through a dedicated hardware bridge, such as a bridge through a level-zero cache coupled with the coherency hardware.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.