Testing hierarchical address translation with context switching and overwritten table definition data
US11138126B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 24, 2019 |
| Grant date | Oct 5, 2021 |
| Priority date | — |
| Expiry date | Jul 20, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/684
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Data processing apparatus comprises one or more processing elements to execute processing instructions; address translation circuitry to perform address translations between a virtual address space and a physical address space, the address translations being defined by a current hierarchical set of address translation tables selected from two or more hierarchical sets of address translation tables, the address translation circuitry being responsive to current table definition data providing at least a pointer to a memory location of the current hierarchical set of address translation tables; the one or more processing elements being configured to overwrite the current table definition data with second table definition data providing at least a pointer to a memory location of a second, different, hierarchical set of address translation tables of the two or more hierarchical sets of address translation tables; the one or more processing elements being configured to execute test instructions requiring address translation before and after the overwriting of the current table definition data by the control circuitry and to detect whether the address translations required by the test ins…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.