Memory cell device and method for operating a memory cell device
US11139003B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 12, 2019 |
| Grant date | Oct 5, 2021 |
| Priority date | — |
| Expiry date | Dec 12, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2227
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In accordance with an embodiment, a memory cell device includes at least one memory cell; a first switch connected between the at least one memory cell and a reference potential node; a second switch connected between the at least one memory cell and the reference potential node, and switch driver logic adapted to put the first switch selectively into one of at least three operating states by activation or deactivation of a first subcircuit of the switch driver logic, wherein the at least three operating states comprises an on state, an off state, and a conductive state in which an electrical conductivity of the first switch is lower than in the on state and higher than in the off state, and put the second switch selectively into one of the at least three operating states by activation or deactivation of a second subcircuit of the switch driver logic.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.