Semiconductor package
US11139251B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 3, 2019 |
| Grant date | Oct 5, 2021 |
| Priority date | — |
| Expiry date | Oct 3, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/96
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package includes a semiconductor chip having an active surface on which a connection pad is disposed and an inactive surface opposing the active surface, a first encapsulant covering at least portions of the inactive surface and a side surface of the semiconductor chip, a connection structure having first and second regions disposed sequentially on the active surface of the semiconductor chip, and including a redistribution layer electrically connected to the connection pad of the semiconductor chip and including a ground pattern layer, and a metal layer disposed on the upper surface of the first encapsulant, and extending from the upper surface of the first encapsulant to the side surface of the first region of the connection structure. The first region of the connection structure has a first width, and the second region has a second width, smaller than the first width.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.