Low power flip-flop with balanced clock-to-Q delay
US11139803B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 23, 2020 |
| Grant date | Oct 5, 2021 |
| Priority date | — |
| Expiry date | Sep 23, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/1565
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Systems, apparatuses, and methods for implementing low-power flip-flops with balanced clock-to-Q delay are described. A flip-flop includes a primary latch, an upper secondary latch, and a lower secondary latch. The primary latch transmits a data value from an input port to a first node when transparent. The upper secondary latch pulls up a second node when transparent and when the first node is equal to a first value. The second node is a prebuffered data output of the flip-flop. The lower secondary latch pulls down the second node when transparent and when the first node is equal to a second value different from the first value. To ensure the flip-flop has a balanced clock-to-Q delay, a first set of clock signals coupled to transistor gates of the primary latch are delayed with respect to a second set of clock signals coupled to transistor gates of the upper secondary latch.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.