Hardware based technique to prevent critical fine-grained cache side-channel attacks
US11144468B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 29, 2018 |
| Grant date | Oct 12, 2021 |
| Priority date | — |
| Expiry date | Jun 29, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/281
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system may include a processor and a memory, the processor having at least one cache. The cache may include a plurality of sets, each set having a plurality of cache lines. Each cache line may include several bits for storing information, including at least a “shared” bit to indicate whether the cache line is shared between different processes being executed by the processor. The example cache may also include shared cache line detection and eviction logic. During normal operation, the cache logic may monitor for a context switch (i.e., determine if the processor is switching from executing instructions for a first process to executing instructions for a second process). Upon a context switch, the cache logic may evict the shared cache lines (e.g., the cache lines with a shared bit of 1). This eviction of shared cache lines may prevent attackers utilizing such attacks from gleaning meaningful information.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.