Atomic instruction having a local scope limited to an intermediate cache level
US11144480B2 · kind B2 · utility
1Cited by
2References
10Claims
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Key dates
| Filing date | Mar 7, 2017 |
| Grant date | Oct 12, 2021 |
| Priority date | — |
| Expiry date | Nov 21, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/621
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention relates to a method for updating a variable shared between multiple processor cores. The following steps are implemented during execution in one of the cores of a local scope atomic read-modify-write instruction (AFA), having a memory address (a1) of the shared variable as a parameter: performing operations of the atomic instruction in a cache line (L(a1)) allocated to the memory address; and locally locking the cache line (LCK) while authorizing access to the shared variable by cores connected to another cache memory of same level during execution of the local scope atomic instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.