Patent · US Active

Method and apparatus for digital only secure test mode entry

US11144677B2 · kind B2 · utility

2Cited by

4References

21Claims

0Family size

Assignee

NXP USA, Inc. · US

Inventors

Stefan Doll · Obermoschel, DE
Thomas Henry Luedeke · Oberbergkirchen, DE
Nikila Krishnamoorthy · Chennai, IN
Hubert Glenn Carson, Jr. · Austin, US
Anurag Jindal · Singapore, SG
Hilario Manuel Garza · Cedar Park, US
Kamel Musa Khalaf · Austin, US
Joel Ray Knight · Austin, US
Adrian Lee Carleton · Austin, US

Key dates

Filing date	Aug 8, 2019
Grant date	Oct 12, 2021
Priority date	—
Expiry date	Apr 23, 2040

Classification

Technology area (CPC G)Physics
CPC primaryG06F2221/2103
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A fully digital integrated circuit apparatus (200) and method (300) are provided for generating a test mode enable signal with a digital non-resettable state retention storage circuit (210) connected to store an authentication control pattern for authorizing test mode access to a secure circuit, a digital safety interlock gate circuit (220) connected to store a safety interlock gate setting that may be accessed independently from a test mode enable signal, and combinatorial logic circuitry (205) for generating the test mode enable signal only when the interlock safety gate setting is set to a first value and the digital non-resettable state retention storage circuit stores the authentication control code.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.