Anurag Jindal
34Patents
5h-index
58Co-inventors
68Inventor score
Filing activity: Mar 23, 2011 → Oct 6, 2021
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US9599672B2 | Integrated circuit with scan chain having dual-edge triggered scannable flip flops and method of operating thereof | Physics | 17 | Active |
| US9297855B1 | Integrated circuit with increased fault coverage | Physics | 13 | Active |
| US8841952B1 | Data retention flip-flop | Electricity | 8 | Active |
| US9568551B1 | Scan wrapper circuit for integrated circuit | Physics | 7 | Active |
| US9766289B2 | LBIST debug controller | Physics | 5 | Active |
| US9298572B2 | Built-in self test (BIST) with clock control | Physics | 4 | Active |
| US9099442B2 | Conductive interconnect structures incorporating negative thermal expansion materials and associated systems, devices, and methods | Electricity | 4 | Active |
| US9034752B2 | Methods of exposing conductive vias of semiconductor devices and associated structures | Emerging Cross-Sectional Technologies | 3 | Active |
| US9754825B2 | Conductive interconnect structures incorporating negative thermal expansion materials and associated systems, devices, and methods | Electricity | 3 | Active |
| US9773807B1 | Conductive components and memory assemblies | Electricity | 3 | Active |
| US9213063B2 | Reset generation circuit for scan mode exit | Physics | 3 | Active |
| US9285424B2 | Method and system for logic built-in self-test | Physics | 2 | Active |
| US11144677B2 | Method and apparatus for digital only secure test mode entry | Physics | 2 | Active |
| US8956974B2 | Devices, systems, and methods related to planarizing semiconductor devices after forming openings | Electricity | 2 | Active |
| US8872252B2 | Multi-tiered semiconductor apparatuses including residual silicide in semiconductor tier | Electricity | 2 | Active |
| US10014319B1 | Conductive components and memory assemblies | Electricity | 1 | Active |
| US8871103B2 | Process of planarizing a wafer with a large step height and/or surface area features | Electricity | 1 | Active |
| US9922875B2 | Conductive interconnect structures incorporating negative thermal expansion materials and associated systems, devices, and methods | Electricity | 1 | Active |
| US8580690B2 | Process of planarizing a wafer with a large step height and/or surface area features | Electricity | 1 | Active |
| US9627295B2 | Devices, systems and methods for manufacturing through-substrate vias and front-side structures | Electricity | 1 | Active |
| US10546777B2 | Conductive interconnect structures incorporating negative thermal expansion materials and associated systems, devices, and methods | Electricity | 1 | Active |
| US8911558B2 | Post-tungsten CMP cleaning solution and method of using the same | Chemistry; Metallurgy | 1 | Active |
| US10847442B2 | Interconnect assemblies with through-silicon vias and stress-relief features | Electricity | 1 | Active |
| US9599673B2 | Structural testing of integrated circuits | Physics | 1 | Active |
| US9201116B1 | Method of generating test patterns for detecting small delay defects | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.