Extensible layer mapping for in-design verification
US11144690B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 18, 2019 |
| Grant date | Oct 12, 2021 |
| Priority date | — |
| Expiry date | Dec 18, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques and systems for implementing a general extensible layer mapping approach that maps between integrated circuit (IC) design database layers and process layers are described. A first IC design layout having in-design layers can be converted into a second IC design layout having derived layers, wherein said converting comprises mapping the in-design layers to the derived layers by applying a set of layer derivation rules to shapes in the IC design layout, and wherein the set of layer derivation rules implements a one-to-many mapping between the in-design layers and the derived layers. Next, a one-to-one mapping between the derived layers and process layers used in a parasitic extraction tool can be generated. Parasitic extraction on the IC design layout then be performed by providing the second IC design layout and the one-to-one mapping to the parasitic extraction tool.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.