Memory with adjustable TSV delay
US11145352B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 6, 2019 |
| Grant date | Oct 12, 2021 |
| Priority date | — |
| Expiry date | Dec 6, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/06565
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Memory devices and systems with adjustable through-silicon via (TSV) delay, and associated methods, are disclosed herein. In one embodiment, an apparatus includes a plurality of memory dies and a TSV configured to transmit signals to or receive signals from the plurality of memory dies. The apparatus further includes circuitry coupled to the TSV and configured to introduce propagation delay onto signals transmitted to or received from the TSV. In some embodiments, the apparatus includes additional circuitry configured to activate, deactivate, adjust at least a portion of the circuitry, or any combination thereof, to alter the propagation delay. In this manner, the apparatus can align internal timings of memory dies of the plurality of memory dies.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.