Patent · US Active

Silicon-on-insulator substrate including trap-rich layer and methods for making thereof

US11145537B2 · kind B2 · utility

0Cited by

2References

7Claims

0Family size

Assignee

Addison Crockett · US

Inventors

Ron Bowman · Chandler, US
Mark Franklin · Scotts Valley, US

Key dates

Filing date	Oct 7, 2020
Grant date	Oct 12, 2021
Priority date	—
Expiry date	Oct 7, 2040

Classification

Technology area (CPC H)Electricity
CPC primaryH10D86/201
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A silicon-on-insulator substrate includes: (1) a high-resistivity base layer including silicon and a trap-rich region including arsenic diffused within a first side of the high-resistivity base layer, wherein the trap-rich region has a thickness that is in a range of 1 to 10 microns and a trap density that is in a range of 0.8*1010 cm2 eV−1 to 1.2*1010 cm2 eV−1, wherein the high-resistivity base layer has resistivity in a range of 50 to 100 ohm-meters and a thickness in a range of 500 to 700 microns; (2) a silicon dioxide layer positioned on the first side of the high-resistivity base layer and having a thickness that is in a range of 1000 to 5000 angstroms; and (3) a transfer layer positioned on the silicon dioxide layer, wherein the transfer layer comprises a silicon wafer having a thickness that is a range of 500 to 5000 angstroms.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.