High resistivity silicon-on-insulator structure and method of manufacture thereof
US11145538B2 · kind B2 · utility
4Cited by
23References
24Claims
0Family size
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Key dates
| Filing date | Sep 25, 2019 |
| Grant date | Oct 12, 2021 |
| Priority date | — |
| Expiry date | Apr 24, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/693
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A multilayer structure is provided, the multilayer structure comprising a semiconductor on insulator structure comprises an insulating layer that enhances the stability of the underlying charge trapping layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.