Global dielectric and barrier layer
US11145542B2 · kind B2 · utility
0Cited by
7References
20Claims
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Key dates
| Filing date | Jul 15, 2019 |
| Grant date | Oct 12, 2021 |
| Priority date | — |
| Expiry date | Jul 15, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device including a substrate having a dielectric layer over the substrate and a first conductive feature disposed within the dielectric layer. A metal nitride material is disposed directly on a top surface of the first conductive feature. A metal oxynitride material is disposed directly on a top surface of the dielectric layer, wherein the metal nitride and the metal oxynitride are coplanar. A second conductive feature is disposed over and interfacing the metal nitride material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.