Multi-layer passivation structure and method
US11145564B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 26, 2019 |
| Grant date | Oct 12, 2021 |
| Priority date | — |
| Expiry date | Apr 26, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/00014
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Semiconductor devices, integrated circuits and methods of forming the same are provided. In one embodiment, a method for integrated circuit (IC) fabrication includes forming a passivation layer over a first contact feature, forming a second contact feature over and through the passivation layer to electrically connect to the first contact feature, and forming a multi-layer passivation structure over the second contact feature and over the passivation layer. Forming the multi-layer passivation structure includes depositing a first nitride layer, an oxide layer over the first nitride layer, and a second nitride layer over the oxide layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.