Memory device and multi-level memory cell having ferroelectric storage element and magneto-resistive storage element
US11145676B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 22, 2020 |
| Grant date | Oct 12, 2021 |
| Priority date | — |
| Expiry date | May 22, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N50/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a plurality of word lines, a plurality of bit lines, a plurality of source lines and a plurality of multi-level memory cells is introduced. Each of the multi-level memory cells is coupled to one of the word lines, one of the bit lines and one of the source lines. Each of the multi-level memory cells includes a ferroelectric storage element and a magneto-resistive storage element cascaded to the ferroelectric storage element. The ferroelectric storage element is configured to store a first bit of a multi-bit data. The magneto-resistive storage element is configured to store a second bit of the multi-bit data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.