Low-latency retimer with seamless clock switchover
US11150687B1 · kind B1 · utility
3Cited by
1References
21Claims
0Family size
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Key dates
| Filing date | Jul 10, 2020 |
| Grant date | Oct 19, 2021 |
| Priority date | — |
| Expiry date | Jul 10, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00019
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A low-latency signaling link retimer generates an output signal transmission synchronously with respect to a core clock signal alternately selected from two or more plesiochronous or mesochronous clock sources with switchover between or among the core-clock sources executed without shrinking, extending or otherwise disrupting the edge-to-edge core clock period or clock duty cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.