Memory system and method of operating the memory system
US11150838B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 11, 2019 |
| Grant date | Oct 19, 2021 |
| Priority date | — |
| Expiry date | Dec 19, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/26
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present technology includes a memory system and a method of operating the memory system. The memory system includes a memory device including an interface circuit and a semiconductor memory, and a controller configured to generate a command set in response to a host command and output the command set to the memory device. The interface circuit is configured to: receive the command set, transmit the received command set to the semiconductor memory, when the received command set corresponds to the semiconductor memory, perform a blocking operation so that the received command set is not transmitted to the semiconductor memory, when the received command set corresponds to the interface circuit, and perform an on-die termination operation, a ZQ calibration operation, or a driving force control operation of the interface circuit in response to the received command set corresponding to the interface circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.