Three-dimensional memory device with a dielectric isolation spacer and methods of forming the same
US11152284B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 7, 2020 |
| Grant date | Oct 19, 2021 |
| Priority date | — |
| Expiry date | May 7, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory stack structures extending through the alternating stack are formed. A backside trench is formed through the alternating stack. The sacrificial material layers are replaced with electrically conductive layers. An insulating spacer and the backside contact via structure are formed within the backside trench. A dielectric isolation trench is formed by removing a peripheral portion of an upper region of the backside contact via structure and an upper portion of the insulating spacer. A dielectric isolation spacer is formed in the dielectric isolation trench to prevent an electrical short between an upper portion of the backside contact via structure and the electrically conductive layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.