Semiconductor package including a redistribution line
US11152416B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 10, 2019 |
| Grant date | Oct 19, 2021 |
| Priority date | — |
| Expiry date | Jul 10, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F39/026
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package includes a first semiconductor chip. A second semiconductor chip is below the first semiconductor chip. A third semiconductor chip is below the second semiconductor chip. The second semiconductor chip includes a first surface in direct contact with the first semiconductor chip, and a second surface facing the third semiconductor chip. A first redistribution pattern is on the second surface of the second semiconductor chip and is electrically connected to the third semiconductor chip. The third semiconductor chip includes a third surface facing the second semiconductor chip. A conductive pad is on the third surface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.