Drain extended transistor
US11152505B2 · kind B2 · utility
1Cited by
29References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 28, 2018 |
| Grant date | Oct 19, 2021 |
| Priority date | — |
| Expiry date | Nov 14, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/371
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Described examples include integrated circuits, drain extended transistors and fabrication methods in which an oxide structure is formed over a drift region of a semiconductor substrate, and a shallow implantation process is performed using a first mask that exposes the oxide structure and a first portion of the semiconductor substrate to form a first drift region portion for connection to a body implant region. A second drift region portion is implanted in the semiconductor substrate under the oxide structure by a second implantation process using the first mask at a higher implant energy.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.