Dynamic modification of instructions that do not modify the architectural state of a processor
US11157285B2 · kind B2 · utility
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30References
18Claims
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Key dates
| Filing date | Feb 6, 2020 |
| Grant date | Oct 26, 2021 |
| Priority date | — |
| Expiry date | Feb 6, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/6028
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method including a processor configured to, based on encountering an instruction that does not modify the architectural state of the processor, preferably a prefetch instruction, that is being executed by the processor, determine whether utilization of a first queue used in processing the instruction is over a first queue utilization limit; in response to the first queue utilization being over the first queue utilization limit, do not execute the prefetch instruction; and in response to the first queue utilization being under the first queue utilization limit, at least partially process the prefetch instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.