Implementing atomic primitives using cache line locking
US11157407B2 · kind B2 · utility
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5References
18Claims
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Key dates
| Filing date | Dec 14, 2017 |
| Grant date | Oct 26, 2021 |
| Priority date | — |
| Expiry date | Dec 14, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/62
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor comprising a cache, the cache comprising a cache line, an execution unit to execute an atomic primitive to responsive to executing a read instruction to retrieve a data item from a memory location, cause to store a copy of the data item in the cache line, execute a lock instruction to lock the cache line to the processor, execute at least one instruction while the cache line is locked to the processor, and execute an unlock instruction to cause the cache controller to release the cache line from the processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.