Memory cell arrangement and methods thereof
US11158361B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 8, 2020 |
| Grant date | Oct 26, 2021 |
| Priority date | — |
| Expiry date | May 8, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B51/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory cell arrangement is provided that may include: a plurality of memory cells including one or more memory cells to be read out and one or more memory cells not to be read out; a control circuit defining a base voltage and configured to: apply a select voltage, a first readout voltage and a second readout voltage, to one word-line and to a source/bit-line pair corresponding to the one or more memory cells to be read out, respectively; apply a voltage that is substantially the base voltage to one or more word-lines corresponding to the one or more memory cells not to be read out; wherein both the first readout voltage and the second readout voltage are provided with an offset to the base voltage, and wherein the first readout voltage and the second readout voltage are different from one another.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.