Operation method for 3D NAND flash and 3D NAND flash
US11158383B2 · kind B2 · utility
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Key dates
| Filing date | May 11, 2020 |
| Grant date | Oct 26, 2021 |
| Priority date | — |
| Expiry date | May 11, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An operation method for a 3D NAND flash having a plurality of bit lines, wherein the plurality of bit lines comprises a plurality of layers, the operation method includes defining a plurality of upper layers of the plurality of bit lines of the 3D NAND flash as a plurality of upper select gates and a top layer of the plurality of bit lines of the 3D NAND flash as a top dummy layer; and applying a first voltage on a first top dummy layer of a select bit line of the plurality of bit lines to turn on the first top dummy layer of the select bit line of the plurality of bit lines when programming.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.