Techniques for determining memory cell read offsets
US11158387B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 29, 2020 |
| Grant date | Oct 26, 2021 |
| Priority date | — |
| Expiry date | Jul 29, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5632
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods, systems, and devices for techniques for determining memory cell read offsets are described to support determining voltage offsets and corresponding read voltage levels for one or more memory cell levels using a relationship between read voltage levels and voltage offsets. A memory device may estimate first voltage offsets using a first procedure and may perform a read operation using the first voltage offsets. If a first voltage offset results in a read error for a corresponding memory cell level, the memory device may determine an updated voltage offset using the relationship. The relationship may predict a voltage offset for a given read voltage level, such that the memory device may use the relationship to predict an updated voltage offset for a memory cell level. The memory device may use the updated voltage offset(s) to perform a second read operation for the one or more memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.