Semiconductor devices having electrostatic discharge layouts for reduced capacitance
US11158570B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 10, 2018 |
| Grant date | Oct 26, 2021 |
| Priority date | — |
| Expiry date | May 10, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/921
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Semiconductor devices having busing layouts configured to reduce on-die capacitance are disclosed herein. In one embodiment, a semiconductor device includes an electrostatic discharge device electrically connected in parallel with an integrated circuit and configured to divert high voltages generated during an electrostatic discharge event away from the integrated circuit. The semiconductor device further includes a signal bus and a power bus electrically connected to the electrostatic discharge device. The signal bus includes a plurality of first fingers grouped into first groups and the power bus includes a plurality of second fingers grouped into second groups. The first groups are positioned generally parallel to and interleaved between the second groups.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.