Three-dimensional memory devices
US11158622B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 14, 2020 |
| Grant date | Oct 26, 2021 |
| Priority date | — |
| Expiry date | Sep 14, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a peripheral circuit on the substrate, a memory stack including interleaved conductive layers and dielectric layers above the peripheral circuit, a P-type doped semiconductor layer above the memory stack, an N-well in the P-type doped semiconductor layer, a plurality of channel structures each extending vertically through the memory stack into the P-type doped semiconductor layer, a conductive layer in contact with upper ends of the plurality of channel structures, at least part of which is on the P-type doped semiconductor layer, a first source contact above the memory stack and in contact with the P-type doped semiconductor layer, and a second source contact above the memory stack and in contact with the N-well.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.