Cascode cell
US11158624B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 24, 2020 |
| Grant date | Oct 26, 2021 |
| Priority date | — |
| Expiry date | Apr 24, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2200/75
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to semiconductor structures and, more particularly, to unitary Cascode cells with resistance and capacitance optimization, and methods of manufacture. The structure includes a common source FET (CS-FET) in a first portion of a single common semiconductor region, the CS-FET comprising a source region and a drain region, a common gate FET (CG-FET) in a second portion of the single common semiconductor region, the CG-FET comprising a source region and a drain region, and a doped connecting region of the single common semiconductor region, connecting the drain of the CS-FET and the source of the CG-FET.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.