Multi-level isolation structure
US11158633B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 7, 2020 |
| Grant date | Oct 26, 2021 |
| Priority date | — |
| Expiry date | Apr 7, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/853
Abstract
One illustrative device disclosed herein includes at least one fin structure and an isolation structure comprising a stepped upper surface comprising a first region and a second region. The first region has a first upper surface and the second region has a second upper surface, wherein the first upper surface is positioned at a first level and the second upper surface is positioned at a second level and wherein the first level is below the second level. In this illustrative example, the device also includes a gate structure comprising a first portion and a second portion, wherein the first portion of the gate structure is positioned above the first upper surface of the isolation structure and above the at least one fin structure and wherein the second portion of the gate structure is positioned above the second upper surface of the isolation structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.