Inventor · Clifton Park, NY, US

Haiting Wang

131Patents
8h-index
197Co-inventors
79Inventor score

Filing activity: Dec 17, 2009 → Oct 7, 2024

Most-cited inventions

PatentTitleAreaCited byStatus
US9653583B1 Methods of forming diffusion breaks on integrated circuit products comprised of finFET devices Electricity 52 Active
US8324668B2 Dummy structure for isolating devices in integrated circuits Electricity 29 Active
US10083874B1 Gate cut method Electricity 23 Active
US8502316B2 Self-aligned two-step STI formation through dummy poly removal Electricity 21 Active
US9425100B1 Methods of facilitating fabricating transistors Electricity 13 Active
US8722485B1 Integrated circuits having replacement gate structures and methods for fabricating the same Electricity 12 Active
US9935104B1 Fin-type field effect transistors with single-diffusion breaks and method Electricity 9 Active
US10388652B2 Intergrated circuit structure including single diffusion break abutting end isolation region, and methods of forming same Electricity 9 Active
US10373877B1 Methods of forming source/drain contact structures on integrated circuit products Electricity 8 Active
US9331159B1 Fabricating transistor(s) with raised active regions having angled upper surfaces Electricity 7 Active
US9418899B1 Method of multi-WF for multi-Vt and thin sidewall deposition by implantation for gate-last planar CMOS and FinFET technology Electricity 6 Active
US9443771B1 Methods to thin down RMG sidewall layers for scalability of gate-last planar CMOS and FinFET technology Electricity 6 Active
US10396206B2 Gate cut method Electricity 4 Active
US10586860B2 Method of manufacturing finfet devices using narrow and wide gate cut openings in conjunction with a replacement metal gate process Electricity 4 Active
US10153209B1 Insulating gate separation structure and methods of making same Electricity 4 Active
US10192746B1 STI inner spacer to mitigate SDB loading Electricity 4 Active
US8535998B2 Method for fabricating a gate structure Electricity 4 Active
US10522410B2 Performing concurrent diffusion break, gate and source/drain contact cut etch processes Electricity 4 Active
US9984933B1 Silicon liner for STI CMP stop in FinFET Electricity 3 Active
US10586736B2 Hybrid fin cut with improved fin profiles Electricity 3 Active
US10707303B1 Method, apparatus, and system for improving scaling of isolation structures for gate, source, and/or drain contacts Electricity 3 Active
US8368147B2 Strained semiconductor device with recessed channel Electricity 2 Active
US8633070B2 Lightly doped source/drain last method for dual-epi integration Electricity 2 Active
US9312145B2 Conformal nitridation of one or more fin-type transistor layers Electricity 2 Active
US10373875B1 Contacts formed with self-aligned cuts Electricity 2 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.